Khaled Salah, Yehea Ismail, Visit Amazon's Alaa El-Rouby's Arbitrary Modeling of TSVs for 3D Integrated Circuits PDF

By Khaled Salah, Yehea Ismail, Visit Amazon's Alaa El-Rouby Page, search results, Learn about Author Central, Alaa El-Rouby,

ISBN-10: 3319076108

ISBN-13: 9783319076102

ISBN-10: 3319076116

ISBN-13: 9783319076119

This ebook provides a wide-band and know-how self sustaining, SPICE-compatible RLC version for through-silicon vias (TSVs) in 3D built-in circuits. This version money owed for various results, together with epidermis impression, depletion capacitance and within sight touch results. Readers will reap the benefits of in-depth insurance of options and expertise comparable to 3D integration, Macro modeling, dimensional research and compact modeling, in addition to closed shape equations for the via silicon through parasitics. options lined are validated through the use of TSVs in purposes akin to a spiral inductor and inductive-based communique approach and bandpass filtering.

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Extra info for Arbitrary Modeling of TSVs for 3D Integrated Circuits

Example text

Friedman, Three-Dimensional Integrated Circuit Design (Elsevier, 2011) 9. A. Papanikolaou, D. Soudris, R. Radojcic, Three Dimensional System Integration (Springer, New York, 2011) 10. C. Ryu, J.  351–354 11. C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, J.  215–220 12. M. Jang, C. Y. H. Cho, J. S. J. Lee, J. Yu, Development and evaluation of 3-D SiP with vertically interconnected through silicon vias (TSV), in Proc.  847–852 13. C. Ryu, J. S. Pak, Multi-stacked through-silicon-via effects on signal integrity and power integrity for application of 3-dimensional stacked-chip-package, in IEEE, 2009 14.

46. 47. 48. 49. 50.  562–567 C. Ferri, S. Reda, I. Bahar, Parametric yield management for 3D ICs: models and strategies for improvement. ACM J. Emerg. Technolog. Comp. Syst. 4, 22 (2008) M. Hogan, D. Petranovic, Robust verification of 3D-ICs: pros, cons and recommendations, in 3D System Integration, 2009, 3DIC 2009 (2009) T. Bandyopadhyay, K. Han, D. Chung, R. Chatterjee, M. Swaminathan, R. Tummala, Rigorous electrical modeling of through silicon vias (TSVs) with MOS capacitance effects. IEEE Trans.

The comparison shows a 5 % difference between the two methods where the difference is calculated using log function. The error is deemed acceptable; hence, the quasi-static simulator is used in the rest of this book.

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Arbitrary Modeling of TSVs for 3D Integrated Circuits by Khaled Salah, Yehea Ismail, Visit Amazon's Alaa El-Rouby Page, search results, Learn about Author Central, Alaa El-Rouby,


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